TPU SoC Design Engineer, Cloud

Job description

Define and document the microarchitecture for digital designs within the TPU. Develop high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog. Partner with the Verification team to develop test plans, debug RTL, and ensure functional correctness. Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements. Contribute to the development and enhancement of design tools, flows, and methodologies. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 2 years of experience architecting RTL solutions employing software based construction, instantiation, customization or generation of RTL. Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with scripting languages (i.e. Tcl, Python or Perl). Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL. Experience with SOC implementation standards and interfaces (i.e. AXI). Experience with CDC, RDC, RTL Linting and LEC. Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.