Physical Low Power Validation Engineer

Job description

Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in post-layout physical netlist validation or low-power signoff in an ASIC design environment. Experience in static low-power rule checking tools (e.g., VCLP or CLP) or debugging signal corruption or structural checks. Experience debugging technical issues within the IEEE 1801 UPF framework or the physical gate-level netlist flow. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience interacting with Place and Route (P&R) tools (Innovus, Fusion) and an understanding of standard cell timing, hierarchical construction, and physical logic optimization. Familiarity with the behavioral nuances of timing-driven P&R algorithms, specifically regarding the insertion, scaling, level shifters and always-on (AON) cells in modern process nodes. Effective skills with scripting languages such as Tcl or Python to automate Engineering Change Orders (ECOs) and improve verification workflows.