ASIC Formal Verification Engineer, TPU Compute

Job description

Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques. Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects. Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans. Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics. Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in silicon development or ASIC/SoC design. Experience with SystemVerilog Assertions (SVA) and formal verification methods. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture. 10 years of experience with industry standard tools, languages, and methodologies relevant to the development of silicon-based ICs and chips. Experience with one or more formal verification platforms (e.g., Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal). Experience in formal verification applications such as data-path verification, sequential equivalence checking, and connectivity checking. Experience in formally proving correctness of arithmetic units such as floating point adders and multipliers. Experience working with schedulers, NOCs and networking topologies, protocols (AXI/AMBA).