Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects

Job description

Lead the microarchitecture and RTL execution to deliver high-performance network design components which meet strict power, performance and area (PPA) goals and satisfy established coding and quality guidelines. Collaborate with system architects and software/firmaware teams to ensure alignment between system and IP requirements. Own the complete RTL lifecycle from initial microarchitecture, coding and documentation to ensuring sign-off readiness for Lint, CDC, and synthesis. Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness. Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience with high-speed interconnects. Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 7 years of experience in high-performance ASIC design. Experience with IEEE networking standards and applications. Experience with scripting languages (e.g., Tcl, Python or Perl). Familiarity with one or more industry-standard tools for CDC, RDC, RTL Linting, or LEC. Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.