Chip Package Signal and Power Integrity Engineer

Job description

Drive chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for HPC based on 2.5D/3D package technology. Develop Power integrity methodology for advanced package technology, and Methodology development to enhance accuracy and productivity. Evaluate New package technology and development, and High speed Interface IP. Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design target, define boundaries of chip design and explore SI/PI and DFM trad-eoff for package design closure for production. Provide feedback on chip floorplan considering package/system routability and SI/PI. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with SI/PI design for chip/package or system PCB. Experience in industry Signal integrity and Power Integrity (SIPI) modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.). Preferred Qualifications: Master’s degree or PhD in Electrical Engineering or SI/PI. Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, and expertise in SI/PI analysis for high-speed interconnects. Knowledge of next-generation memory and chiplet standards, including timing budget, design & sign-off methodologies. Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design. Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams. Proficient in Python, Matlab, or C++ to establish automation flows and advanced data processing/analysis.