Senior SoC Chiplet Architect

Job description

Job Details: Job Description: About the Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. We are seeking a Senior SoC Chiplet Architect to define and lead the architecture strategy for multi-generation, chiplet-based SoC platforms targeting next-generation data center workloads. This role is responsible for chiplet partitioning, die-to-die (D2D) interconnect architecture, and system-level tradeoff analysis across performance, power, area (PPA), cost/yield, and software complexity. You will drive modular, scalable SoC design approaches, including cross-chiplet coherency, system infrastructure (boot/reset/telemetry), and RAS/security architectures across multi-die systems. What You’ll Do Key responsibilities will include but not limited to: Chiplet Architecture Strategy and Roadmap1. Define the monolithic vs. chiplet decision framework and multi-generation roadmap, incorporating reticle scaling limits, yield economics, modularity, and portfolio reuse strategy2. Lead architecture studies for 2-die / 3-die / multi-chiplet scaling (compute + I/O/network + memory/accelerators), including partition boundaries, SKU scalability, and future-proof modular upgrades3. Produce executive-ready architecture options and recommendations for leadership decisions (build/partner/standardize)Chiplet Partition, Resource Scaling, and System Topology1. Drive functional partitioning across chiplets (compute, networking/I/O, accelerators, memory controllers, security/management), balancing PPA, D2D bandwidth/latency, validation complexity, and product flexibility2. Define scalable system resource models (e.g., memory channels, PCIe lanes, pipeline scaling) and how these scale with chiplet count and topology3. Specify any required logic / gaskets and integration constraints to enable modular assembly and consistent SW-visible behaviorDie-to-Die (D2D) Interconnect Architecture and QoS1. Architect D2D communication for high bandwidth, low latency, and reliability across chiplets; define link budgets and requirements for bandwidth, latency, error handling, and flow control2. Define inter-chiplet QoS mechanisms (e.g., arbitration, prioritization, isolation) and ensure the architecture supports workload-driven traffic patterns at scale3. Align D2D choices with industry standardization direction (where applicable) and ensure project-specific needs can be encapsulated cleanlyChiplet System Infrastructure: Power, Clock/Reset, Boot, telemetry1. Define coordinated power delivery and power management flows across chiplets (telemetry, quiescence, package states, throttling), including system-level sequencing and corner cases2. Architect clocking and reset distribution (reference clock delivery, local PLL strategies, reset sequencing, debug/manufacturing hooks) and ensure robust bring-up across all dies3. Drive the chiplet-aware boot and early firmware architecture (e.g., parallel boot considerations, coordinated reset control) in partnership with FW/platform teamsRAS, Debug, and Observability Across Chiplets1. Define cross-chiplet error reporting, containment, and recovery policies, including consistent crashdump, telemetry access, and actionable observability for post-silicon debug2. Specify debug/trace infrastructure assumptions to ensure chiplet partitioning does not compromise lab efficiency or field diagnosabilityQuantitative Trade Off Studies1. Lead quantitative trade studies across performance, power, area, cost/yield, and schedule; identify bottlenecks and propose architecture-level mitigations2. Partner with packaging/manufacturing stakeholders for trade-off comparisons (e.g., explicitly tracking whether packaging overheads are included in a given analysis)Cross-Functional Technical Leadership1. Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams; lead reviews, challenge assumptions, and converge on clear architectural decisions2. Work with other architects and contribute reusable patterns/checklists for chiplet-based SoC infrastructureBehavioral traits that we are looking for: • Strategic vision: Defines long-term chiplet architecture direction across product lines • Complex decision-making: Evaluates multidimensional tradeoffs (PPA, cost, schedule, risk) • Influence at scale: Drives alignment across organizations without direct authority • Systems-level thinking: Understands full-stack implications (hardware, firmware, software, manufacturing) • Executive communication: Translates complex architecture into clear recommendations • Collaboration: Partners effectively across architecture, packaging, and platform teams • Ownership mindset: Leads from concept through productization • Adaptability: Navigates evolving standards and rapidly advancing technologies Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information Minimum Qualifications and Experience:Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.You must have 7 + years of experience in the following:SoC/system architecture, including end-to-end architect