Senior Performance Co-Design Engineer, TPU

Job description

Conduct comprehensive serving performance studies on (current and emerging) LLMs (1P/3P models). Develop and maintain advanced simulation, profiling, and modeling tools to identify bottlenecks, understand key characteristics and project serving workload performance. Partner with model researchers, software and hardware teams to co-design architectural improvements tailored to Large Language Model (LLM) inference latency and throughput. Drive data-backed decisions that influence the roadmap for future TPU/Cloud Silicon architectures. Minimum Qualifications: Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience. 5 years of experience in performance modeling/engineering, computer architecture, co-design, or systems engineering. Experience programming in C++ or Python. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with hardware/software co-design problems, especially performance analysis and identification at the pre-silicon stage. Experience enabling and optimizing large-scale ML models (e.g., LLMs, large embedding models). Experience with ML infrastructure, profiling tools, or deep learning inference/serving optimizations. Familiarity with accelerator architectures.