Staff ASIC Power Engineer, ML Accelerators

Job description

Contribute to design power modeling and drive convergence to power targets. Investigate, spec, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low-power RTL designs. Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets. Be the technical lead of an experienced power team. Own the execution and delivery of complex technical projects end to end. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience in design or architecture (e.g., logic design, power architecture, performance, or SoC design). Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience defining and implementing chip-wide power management architectures and designs. Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases. Experience with technical leadership and project ownership with a track record of successful delivery. Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), Turboing, Thermal Management, and System-Level Tradeoffs). Ability to solve open-ended power and performance problems under ambiguity.