Senior Static Timing Engineer

Job description

Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs. Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations. Develop timing constraint and verify it for sign-off. Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts. Own and maintain Primetime STA flows. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with static timing analysis. Experience in Primetime or Tempus Tcl scripting and static timing analysis debug. Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience writing, reviewing and verifying complex Tcl constraints for static timing analysis. Experience in extraction of design parameters, QoR metrics, and analyzing data trends. Experience working with multiple foundries. Knowledge of semiconductor device physics and transistor characteristics.