Senior Design Verification Engineer, Silicon

Job description

Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience verifying digital logic at RTL using SystemVerilog for ASICs or FPGAs. Experience verifying digital IP and subsystems. Experience working with design verification (DV) testbenches or environments. Preferred Qualifications: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. Experience with verification planning, testplan development, and coverage-driven verification closure. Experience creating and using verification components in VMM, OVM, or UVM. Experience with UPF-based power simulations and gate-level simulation (GLS) debugging. Familiarity with ASIC standard interfaces (e.g., MIPI, ARM AMBA, UART, I2C) and scripting languages like Perl or Python.