Chip Implementation Lead

Job description

Drive technical decisions and synchronization across all implementation domains (physical design, package, power, Signal Integrity and Power Integrity (SI/PI), and DFT, resolving complex cross-functional issues that impact chip delivery. Own the physical implementation of the entire chip, ensuring the final packaged silicon meets all performance, power, area, thermal, yield, and reliability goals. Identify critical blocking issues and implementation risks early, develop and execute mitigation strategies to protect the program schedule and quality. Manage technical interactions with ASIC partners and external vendors to ensure their deliverables align strictly with chip requirements and milestones. Define the framework for implementation execution, including setting technical directions, establishing milestone criteria, and innovation in methodologies. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with silicon implementation with a focus on high-performance SoC or ASIC development. Experience leading cross-functional teams (physical design (PD), package, power, and design for testing through the tape-out cycle, from architecture to Graphic Data System II (GDSII). Experience managing technical relationships with external vendors, ASIC partners, or foundries. Experience with Customer Owned Tooling (COT) design models and the specific tests they present compared to traditional ASIC flows. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 12 years of experience with silicon implementation with a focus on high-performance SoC or ASIC development. Experience defining implementation roadmaps and influencing decisions at the system and architecture level. Experience articulating complex technical risks and status to executive management and cross-functional stakeholders. Deep technical understanding of advanced process nodes, packaging technologies, and the trade-offs between PPA, thermal, and signal integrity. Proven track record of driving complex high-frequency/low-power chips to production with first-pass silicon success.