Senior ASIC DFT Engineer, Silicon

Job description

Minimum Qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 8 years of experience with Design for Test (DFT). Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision, etc). Experience with one more more of the following: Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), and Internal Joint Test Action Group (IJTAG) tools and flow. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. Experience working on DFT for complex subsystems with multiple physical partitions, understanding end-to-end SOC flows (Design, Verification, DFT, PD). Knowledge of high-performance DFT techniques like SSN and HighBandwidth IJTAG, scaling DFT with minimal area overhead. Proficiency with Spyglass-DFT, DFT Scan constraints, evaluating STA paths, and IJTAG (ICL, PDL extraction, and modeling with Siemens Tessent). Proficiency in coverage analysis, Gate-Level Simulation (GLS) debug, and silicon debug. Proficient with a scripting language such as Perl or Python.