Physical Design Lead, ASIC

Job description

Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in physical design, including custom structured datapath implementation. Experience hardening dense compute units (such as dot-product engines, multiplier-accumulator (MACs), multipliers, or arithmetic logic unit (ALUs) into high-frequency, low-power macros. Experience in sub-7nm process nodes (including FinFET and Gate-All-Around architectures), managing the physical density and routing congestion typical of custom datapaths. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture. Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks). Experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation. Experience with physical design and timing, with managing PT-to-PnR timing correlations and metal-fill impacts on dense structures. Expert-level scripting versatility (Tcl, Python, Perl) to build layout automation and structural constraints within standard EDA tools.