Senior Staff Performance Codesign Engineer, TPU

Job description

Define and drive the technical roadmap and architecture for the hardware/software stack, ensuring unparalleled performance for the training and serving of large ML models. Act as the technical liaison between advanced research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency. Architect and oversee the development of next-generation configurable simulation frameworks and cycle-accurate performance models, setting the standard for how the organization evaluates complex micro-architectural decisions. Advocate system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements. Manage cross-functional partnerships across hardware engineering, compiler development, and ML research to influence broad organizational strategy and transition paradigm-shifting concepts into production. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 12 years of experience in computer architecture, chip architecture, or hardware-software co-design. Experience developing systems for performance modeling, simulation, or system analysis. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience as a lead architect driving multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference. Experience with deep learning frameworks (e.g., PyTorch, TensorFlow) and their underlying execution models. Knowledge of semiconductor trajectories, including process, memory, interconnects, and packaging. Understanding of ML trends, business drivers, and the software ecosystem. Ability to engage and align stakeholders, hardware designers, and the global ML research community.