RTL Design Engineer, TPU and ML

Job description

Define and document complex microarchitecture for the TPU, writing high-quality, performant, and power-efficient RTL code primarily in SystemVerilog. Partner with cross-functional teams to drive block-level and chip-level integration efforts for the machine learning accelerators. Collaborate closely with the verification team to develop robust test plans, debug RTL, and guarantee overall functional correctness. Support post-silicon validation and debugging efforts while contributing to the continuous enhancement of internal design tools, flows, and methodologies. Work closely with the physical design team to meet timing, area, power, and manufacturability requirements. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development. Design experience optimizing for performance, power, and area. Experience with digital design fundamentals and microarchitecture design. Experience working cross-functionally with DV and PD teams. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 4 years of RTL design experience. Experience with Linting, CDC, RDC, LEC. Experience with Scripting languages (i.e. Python or Perl). Experience with integration. Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows.