NAND Quality and Reliability R&D Engineer

Job description

NAND array algorithm development and performance/reliability engineering. Key Responsibilities: Design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability. Develop and optimize trims to minimize program and read disturb, directly impacting product quality. Develop and optimize trims to optimize performance and power (tPROGRAM, tREAD, Icc), without impacting reliability and endurance capabilities. Apply NAND device physics principles to explain and interpret relationships between experimental data and trim parameters. Conduct comprehensive data analysis to identify and communicate trade-offs across multiple parameters of interest. Use NAND device physics knowledge and problem-solving skills to design experiments, identify product failure mechanisms, and implement effective solutions. Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams to design, test, and deeply innovative method to improve performance and reliability. Required Qualifications: Bachelor’s in electrical engineering, Microelectronics, or a closely related field. 2+ years of industry experience in semiconductor memory technologies and products. Deep understanding of NAND cell and array operations, including array reliability physical mechanisms and characterization techniques. Strong foundation in semiconductor device physics and process flows. Proficiency in statistical analysis methodologies and tools. Hands-on programming experience in C, C++, Python, and/or JMP. Proven ability to thrive in a fast-paced, cross-functional team environment. Strong analytical and problem-solving skills with attention to detail. Excellent communication and presentation skills, with the ability to convey complex technical concepts to diverse audiences. Preferred Qualifications: Master's or PhD in Electrical Engineering, Microelectronics, or a closely related field. Experience with 3D NAND architecture and advanced memory scaling challenges. Experience in SSD system level FW design and testing