ASIC Design Verification Engineer, Google Cloud

Job description

Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 1 year of experience in design verification. Experience with SystemVerilog/Verilog. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with Universal Verification Methodology (UVM) testbenches and methodologies. Experience developing and executing test plans. Familiarity with coverage analysis tools (e.g., Verdi, Questa). Proficiency in SystemVerilog, including object-oriented programming, SystemVerilog Assertions (SVAs) and functional coverage. Excellent problem-solving and debugging skills.