Standard Cell Design Methodology & Flow Engineer

Job description

Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas and determine how to turn them into reality! You will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking and groundbreaking ideas to the real world. You’ll help design the tools that allow us to bring customers experiences they’ve never-before envisioned. We have an extraordinary opportunity for Standard Cell Design Methodology and Flow Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering quality products to market quickly. Minimum Qualifications: BS and a minimum of 10 years of relevant industry experience Preferred Qualifications: At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc. Experience with timing modeling of large custom macros and complex sequential flops. Exposure to Design For Test, scan concept and write DFT friendly RTL Understands all aspects of implementation specification, design, timing, power, and flow automation. Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation Flow automation skills in standard cells development and integration to improve execution efficiency. Experience of using Python/TCL/Perl Knowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for characterization, synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization. Proven understanding of device physics and process. Familiar with foundry ecosystem and benchmarking practice.