ASIC Design Verification Engineer, TPU

Job description

Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with design verification. Experience with SystemVerilog/Verilog. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 6 years of experience with silicon design verification. Experience contributing across the entire design and verification life cycle. Experience optimizing tools, flows, and methodologies to improve efficiency. Experience with scripting languages (e.g., Python or Perl). Excellent problem-solving and communication skills.