Senior Design and Integration Engineer, Cloud TPU

Job description

Define and document the microarchitecture for digital designs within the TPU. Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals. Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems. Support post-silicon validation and hardware debugging efforts to ensure successful deployment. Lead the development and enhancement of internal design tools, flows, and engineering methodologies. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in RTL design. Experience with digital design and microarchitecture design. Experience in optimizing for performance, power, and area. Cross-functional experience with Design Verification (DV) and Physical Design (PD) teams. Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 10 years of RTL design experience. 4 years of experience in power optimization and experience with power analysis tools like PowerArtist and PTPX. Experience with Linting, CDC, RDC, LEC and experience with Scripting languages (i.e. Python or Perl). Experience optimizing RTL solutions, RTL design methodologies and automate front-end engineering flows. Experience in design automation, architecting RTL solutions and ASIC Synthesis flows.