RTL Design Engineer (TERADYNE, North Reading, MA)

Job description

Opportunity Overview Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products. You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup, and will have cutting-edge AI tools available to optimize your productivity. Responsibilities: - Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect - Integration of industry standard and Teradyne custom IPs - Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success - Providing timing constraints and STA support to the Physical Design team through timing closure - Providing post silicon lab bringup and debug support All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. - BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience. - Extensive logic design experience writing RTL in Verilog - Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT - Experience with logic synthesis and timing constraints - Experience with clock domain crossings (CDC) and static timing analysis (STA) - Experience with high speed memory and serial - Experience with automation through scripting such as Python, Tcl & Make Compensation: The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits: Teradyne offers a variety of comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Job Segment: Electrical Engineering, Developer, Design Engineer, Manufacturing Engineer, Test Engineer, Engineering, Technology